Bits & Chips event 2024
Date: October 10, 2024
Venue: Van der Valk, Best
Bits & Chips event 2024
On 10 October 2024, the fourth edition of the Bits&Chips event will take place at van der Valk Eindhoven-Best.
This year’s edition is actively supported by TNO-ESI. We look forward to meeting you there.
The conference program will cover the following topics:
Generative AI
Machine learning
Software quality
System architecture
ESI presentations:
11.00 What can systems engineering offer to the high-tech equipment industry for continuous innovation?
- Sezen Acur and Bram van der Sanden
11.45 Leveraging large language models for legacy software
- Nan Yang
14.30 Do you still develop supervisory controllers by hand?!
- Wytse Oortwijn and Sjoerd Zwart (VDL-ETG)
Are you interested to visit the event? Please contact us
Sezen Acur
Bram van der Sanden
Nan Yang
Wytse Oortwijn
Sjoerd Zwart (VDL-ETG)
11.00 hrs
Sezen Acur and Bram van der Sanden
What can systems engineering offer to the high-tech equipment industry for continuous innovation?
Systems engineering complexity in the high-tech equipment industry has increased, as the systems themselves steadily evolved with increased functionality and complexity. Current systems have a long lifetime, undergo rapid technological advancement, are increasingly software-intense, and connected to other systems. Growing system complexity, the global competition, successful adoption of new technologies as AI, and scarcity of systems engineers provide challenges to continuous innovation of the high-tech equipment industry.
Improved Systems Architecting and Systems Engineering (SA/SE) methodologies and competence development are needed to address these challenges. TNO-ESI has created an outlook on the required SA/SE capabilities. This presentation provides an overview of identified relevant trends and challenges across the high-tech equipment industry, the derived needs, and a research outlook on what is needed to upgrade their Systems Architecting and Systems Engineering capabilities.
11.45 hrs
Nan Yang
Leveraging large language models for legacy software
Struggling to understand legacy code in your projects? Looking for a way to combine the best of AI and traditional software analysis tools?
We are excited to present a new approach that we're developing at TNO-ESI to tackle these challenges in the high-tech industry!
Legacy code is notoriously difficult to maintain, but it’s essential to the operation of complex systems. Traditional static analysis tools provide reliable insights but require deep, domain-specific knowledge. Meanwhile, Large Language Models (LLMs) are user-friendly but lack precise, in-depth understanding of codebases.
The hybrid method that we are developing aims to bridge this gap by integrating static analysis with LLMs. We extract detailed code insights into a graph database, allowing LLMs to deliver accurate, natural language responses. This approach not only enhances the accuracy of LLMs but also brings a new level of abstraction and user-friendliness to static analysis.
14.30 hrs
Wytse Oortwijn and Sjoerd Zwart (VDL-ETG)
Do you still develop supervisory controllers by hand?!
Supervisory control is a key part of cyber-physical systems, to orchestrate all system resources to work together in a safe, correct and optimal way. Developing supervisory controllers by hand becomes increasingly challenging, for instance due to increasing performance demands, the need to support more and more system variants, shortage of skilled engineers, and so on. In contrast, with Synthesis-Based Engineering (SBE), correct-by-construction supervisory controllers can automatically be computed based on requirement specifications of what the system should do. These are typically much easier to specify than having to work out how the system should realize its requirements in every possible situation, as is done traditionally. SBE has successfully been applied in industry, for example in the semiconductor domain, the industrial printing domain, and the healthcare domain. TNO-ESI is currently investigating the application of SBE together with ASML and VDL-ETG, which we will elaborate upon in this presentation.
Maaike van Leuken, TNO
Automatic formal verification of hardware design
The design of (cryptographic) hardware components in a hardware design language (eg VHDL, Verilog) is a manual task and it is hard to prove that the design adheres to the functional and security requirements. Formal verification can be used to provide guarantees on the security of the mathematical design of cryptography or its software implementation. Some formal verification methods are already applied in the field of hardware design, but these are all manual.
I will talk about our research into automatic formal verification of hardware designs and how these techniques can even automatically generate the VHDL/Verilog code based on the specification.